Stratix Architecture
Figure 2–17. M4K RAM Block Control Signals
Dedicated
8
Row LAB
Clocks
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
alcr_a
clocken_a
renwe_b
clock_b
Local
Local
Interconnect
Interconnect
clock_a
renwe_a
alcr_b
clocken_b
Figure 2–18. M4K RAM Block LAB Row Interface
C4 and C8
Interconnects
R4 and R8
Interconnects
10
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
Byte enable
Clocks
Control
Signals
address
datain
8
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
Altera Corporation
July 2005
2–33
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
