Stratix Architecture
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
widths. Tables 2–5 and 2–6 summarize the possible M4K RAM block
configurations.
Table 2–5. M4K RAM Block Configurations (Simple Dual-Port)
Write Port
Read Port
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1
2K × 2
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1K × 4
512 × 8
256 × 16
128 × 32
512 × 9
256 × 18
128 × 36
v
v
v
v
v
v
v
v
v
Table 2–6. M4K RAM Block Configurations (True Dual-Port)
Port B
512 × 8 256 × 16 512 × 9 256 × 18
Port A
4K × 1
v
2K × 2
v
1K × 4
v
4K × 1
2K × 2
v
v
v
v
v
v
v
v
v
v
v
v
v
1K × 4
v
v
v
512 × 8
256 × 16
512 × 9
256 × 18
v
v
v
v
v
v
v
v
v
v
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
Altera Corporation
July 2005
2–31
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
