Timing Model
Table 4–120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Flip-Chip Packages (Part 2 of 2)
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
SSTL-2 Class II (3)
SSTL-2 Class II (4)
SSTL-2 Class II (5)
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
200
200
150
150
150
250
225
250
225
350
350
350
350
350
200
225
200
200
134
133
133
225
200
225
200
300
300
300
300
300
200
200
167
167
134
133
133
200
200
200
200
250
250
250
250
250
200
200
167
167
134
133
133
200
200
200
200
250
250
250
250
250
200
200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
Differential 1.8-V HSTL
Class I
250
225
225
200
200
200
200
200
MHz
MHz
Differential 1.8-V HSTL
Class II
Differential SSTL-2 (6)
LVPECL (2)
200
500
350
500
350
200
500
350
500
350
167
500
350
500
350
167
500
350
500
350
MHz
MHz
MHz
MHz
MHz
PCML (2)
LVDS (2)
HyperTransport
technology (2)
4–82
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
