DC & Switching Characteristics
Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 2 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
GTL+
250
300
300
300
300
300
300
300
300
300
300
422
422
422
422
422
250
300
200
250
250
250
250
250
250
180
180
180
180
390
390
390
390
390
180
180
200
250
250
250
250
250
250
180
180
180
180
390
390
390
390
390
180
180
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
LVPECL (1)
PCML (1)
LVDS (1)
422
215
422
422
400
200
400
400
400
200
400
400
MHz
MHz
MHz
MHz
HyperTransport
technology (1)
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 1 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
LVTTL
422
422
422
422
390
390
390
390
390
390
390
390
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
Altera Corporation
January 2006
4–79
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
