DC & Switching Characteristics
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Wire-Bond Packages (Part 2 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
LVDS (2)
311
311
275
275
275
275
MHz
MHz
HyperTransport
technology (2)
Table 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Wire-Bond Packages (Part 1 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
LVTTL
200
200
200
200
200
125
125
110
150
90
175
175
175
175
175
100
100
90
175
175
175
175
175
100
100
90
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
133
80
133
80
110
110
110
225
200
225
200
200
200
200
200
200
125
311
400
100
100
100
200
167
200
167
175
175
175
175
175
100
270
311
100
100
100
200
167
200
167
175
175
175
175
175
100
270
311
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
LVPECL (2)
PCML (2)
Altera Corporation
January 2006
4–85
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
