DC & Switching Characteristics
Table 4–121. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Flip-Chip Packages
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
LVTTL
400
400
400
350
400
200
200
167
167
150
150
150
150
250
225
250
225
250
225
400
400
400
300
717
420
717
420
350
350
350
300
350
167
167
150
150
133
133
133
133
225
225
225
225
225
225
350
350
350
250
717
420
717
420
300
300
300
300
300
125
125
133
133
133
133
133
133
200
200
200
200
200
200
300
300
300
200
500
420
500
420
300
300
300
300
300
125
125
133
133
133
133
133
133
200
200
200
200
200
200
300
300
300
200
500
420
500
420
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
LVPECL (2)
PCML (2)
LVDS (2)
HyperTransport
technology (2)
Altera Corporation
January 2006
4–83
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
