Timing Model
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Wire-Bond Packages (Part 1 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
LVTTL
175
175
175
175
175
125
125
110
133
166
133
110
110
167
167
167
167
167
167
175
175
175
125
167
150
150
150
150
150
100
100
90
150
150
150
150
150
100
100
90
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
3.3-V PCI
125
133
100
100
100
167
133
167
133
167
133
150
150
150
100
133
125
133
100
100
100
167
133
167
133
167
133
150
150
150
100
133
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential 1.5-V HSTL
C1
Differential 1.8-V HSTL
Class I
167
167
167
133
167
133
MHz
MHz
Differential 1.8-V HSTL
Class II
Differential SSTL-2 (1)
LVPECL (2)
110
311
250
100
275
200
100
275
200
MHz
MHz
MHz
PCML (2)
4–84
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
