Timing Model
Table 4–116. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Flip-Chip Packages
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
LVTTL
422
422
422
422
422
300
400
400
400
400
400
400
400
400
300
400
422
422
422
422
422
250
350
350
350
350
350
350
350
350
250
350
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL (1)
PCML (1)
LVDS (1)
645
300
645
500
645
275
645
500
640
275
640
450
640
275
640
450
MHz
MHz
MHz
MHz
HyperTransport
technology (1)
Table 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 1 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
LVTTL
422
422
422
422
422
250
390
390
390
390
390
200
390
390
390
390
390
200
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
4–78
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
