DC & Switching Characteristics
The scaling factors for column output pin timing in Tables 4–111 to 4–113
are shown in units of time per pF unit of capacitance (ps/pF). Add this
delay to the tCO or combinatorial timing path for output or bidirectional
pins in addition to the I/O adder delays shown in Tables 4–103 through
4–108 and the IOE programmable delays in Tables 4–109 and 4–110.
Table 4–111. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers Note (1)
Conditions
Parameter
Output Pin Adder Delay (ps/pF)
Value
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL
LVCMOS
24mA
16mA
12mA
8mA
15
25
30
50
60
–
–
–
–
-
–
8
18
25
35
–
–
25
40
–
–
15
20
30
60
Drive Strength
35
80
160
4mA
2mA
75
120
Note to Table 4–111:
(1) The timing information in this table is preliminary.
Table 4–112. Output Delay Adder for Loading on SSTL/HSTL Output Buffers Note (1)
Output Pin Adder Delay (ps/pF)
Conditions
SSTL-3
SSTL-2
SSTL-1.8
1.5-V HSTL
Class I
Class II
25
25
25
20
25
25
25
20
Note to Table 4–112:
(1) The timing information in this table is preliminary.
Table 4–113. Output Delay Adder for Loading on GTL+/GTL/CTT/PCI Output Buffers Note (1)
Conditions Output Pin Adder Delay (ps/pF)
Parameter
Value
GTL+
GTL
CTT
PCI
AGP
VCCIOVoltage
Level
3.3V
2.5V
18
15
18
18
25
-
20
-
20
-
Note to Table 4–113:
(1) The timing information in this table is preliminary.
Altera Corporation
January 2006
4–75
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
