DC & Switching Characteristics
Table 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Flip-Chip Packages (Part 2 of 2)
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
LVDS (1)
645
500
645
500
622
450
622
450
MHz
MHz
HyperTransport
technology (1)
Table 4–115. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Flip-Chip Packages
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
LVTTL
422
422
422
422
422
300
400
400
400
400
400
400
400
400
300
400
422
422
422
422
422
250
350
350
350
350
350
350
350
350
250
350
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
390
390
390
390
390
200
300
300
300
300
300
300
300
300
200
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
Differential 1.5-V HSTL
C1
LVPECL (1)
PCML (1)
LVDS (1)
717
400
717
717
717
375
717
717
640
350
640
640
640
350
640
640
MHz
MHz
MHz
MHz
HyperTransport
technology (1)
Altera Corporation
January 2006
4–77
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
