Timing Model
Table 4–110. Stratix IOE Programmable Delays on Row Pins Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Decrease input delay Off
to internal cells
3,970
3,390
2,810
173
173
3,900
0
4,367
3,729
3,091
181
181
4,290
0
5,022
4,288
3,554
208
208
4,933
0
5,908
5,045
4,181
245
245
5,804
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Small
Medium
Large
On
Decrease input delay Off
to input register
On
Decrease input delay Off
1,240
0
1,364
0
1,568
0
1,845
0
to output register
On
Increase delay to
output pin
Off
On
Off
On
0
0
0
0
397
0
417
0
417
0
417
0
Increase delay to
output enable pin
348
0
383
0
441
0
518
0
Increase output clock Off
enable delay
Small
180
260
260
0
198
286
286
0
227
328
328
0
267
386
386
0
Large
On
Increase input clock
enable delay
Off
Small
Large
On
180
260
260
0
198
286
286
0
227
328
328
0
267
386
386
0
Increase output
enable clock enable
delay
Off
Small
Large
On
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
804
1,512
1,512
0
Increase tZX delay to
output pin
Off
On
1,993
2,092
2,092
2,092
Note to Table 4–109 and Table 4–110:
(1) The delay chain delays vary for different device densities. These timing values only apply to EP1S30 and EP1S40
devices. Reference the timing information reported by the Quartus II software for other devices.
4–74
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
