Timing Model
Table 4–108. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
8 mA
12 mA
4 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
1,571
594
1,650
624
1,650
624
1,650
624
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
208
218
218
218
0
0
0
0
3.3-V LVTTL
2.5-V LVTTL
1,571
1,393
596
1,650
1,463
626
1,650
1,463
626
1,650
1,463
626
562
590
590
590
2,562
1,343
864
2,690
1,410
907
2,690
1,410
907
2,690
1,410
907
945
992
992
992
1.8-V LVTTL
1.5-V LVTTL
6,306
3,369
2,932
9,759
6,830
5,699
–333
591
6,621
3,538
3,079
10,247
7,172
5,984
–350
621
6,621
3,538
3,079
10,247
7,172
5,984
–350
621
6,621
3,538
3,079
10,247
7,172
5,984
–350
621
GTL+
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.5-V HSTL Class I
1.8-V HSTL Class I
267
280
280
280
–346
481
–363
505
–363
505
–363
505
–58
–61
–61
–61
2,207
1,966
1,208
2,317
2,064
1,268
2,317
2,064‘
1,460
2,317
2,064
1,720
4–72
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
