Timing Model
Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
1.5-V LVTTL
2 mA
4 mA
8 mA
5,460
2,690
1,398
6
5,733
2,824
1,468
6
5,733
2,824
1,468
6
5,733
2,824
1,468
6
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
GTL+
CTT
845
887
887
887
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.5-V HSTL Class I
1.8-V HSTL Class I
LVDS
638
670
670
670
144
151
151
151
604
634
634
634
211
221
221
221
955
1,002
769
1,002
769
1,002
769
733
372
390
390
390
–196
–148
–147
–93
–206
–156
–155
–98
–206
–156
–155
–98
–206
–156
–155
–98
LVPECL
PCML
HyperTransport
technology
Note to Table 4–103 through 4–106:
(1) These parameters are only available on row I/O pins.
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
1,822
684
233
1
1,913
718
245
1
1,913
718
245
1
1,913
718
245
1
ps
ps
ps
ps
ps
8 mA
12 mA
24 mA
–608
–638
–638
–638
4–70
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
