Stratix Architecture
Table 2–40. EP1S60 Differential Channels (Part 2 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
1,020-pin
FineLine
BGA
Transmitter 80 (12)
840
12
(2)
10
(4)
10
(4)
12
(2)
20
20
20
10
20
20
10
20
(4)
(7)
22
(6)
22
(6)
22
(6)
22
(6)
20
20
840 (5), (8)
Receiver
80 (10)
840
20
40
20
40
10
20
40
10
20
40
12
(8)
12 (8)
12 (8)
20
(10) (10)
10 10
(10) (10)
(7)
12
(8)
840 (5), (8)
1,508-pin
FineLine
BGA
Transmitter 80 (36)
840
12
(8)
12
(8)
20
20
20
20
10
20
20
10
(10) (10)
(4)
(7)
22
22 22
22
20
840 (5),(8)
(18) (18) (18) (18)
Receiver
80 (36)
840
20
40
20
20
20
40
12
(8)
12 (8)
12 (8)
(10) (10)
10 10
(10) (10)
(7)
40
40
12
(8)
840 (5),(8)
Table 2–41. EP1S80 Differential Channels (Part 1 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
BGA
Transmitter 80 (40)
840
10
20
20
40
10
20
20
40
10
20
20
40
10
20
20
40
20
20
10
10
20
20
20
10
10
20
20
20
10
10
20
20
20
10
10
20
(4)
(7)
840 (5),(8)
840
Receiver
80
840 (5),(8)
840
1,020-pin
FineLine
BGA
Transmitter 92 (12)
10
(2)
10
(4)
10
(4)
10
(2)
(4)
(7)
20
(6)
20
(6)
20
(6)
20
(6)
20
20
20
20
840 (5),(8)
Receiver
90 (10)
(7)
840
20
40
20
40
20
40
20
40
10
(2)
10
(3)
10 (3) 10 (2)
10 (3) 10 (2)
10
(2)
10
(3)
840 (5),(8)
Altera Corporation
July 2005
2–135
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
