Stratix Architecture
Figure 2–75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices Note (1)
Fast
PLL 7
Fast
PLL 10
FPLL7CLK
FPLL10CLK
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Receiver
Transmitter
Receiver
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Receiver
Transmitter
Receiver
Fast
PLL 1
Fast
PLL 4
CLKIN
CLKIN
CLKIN
CLKIN
(3)
(3)
Fast
PLL 2
Fast
PLL 3
Transmitter
Receiver
Transmitter
Receiver
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Receiver
Transmitter
Receiver
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Fast
PLL 8
Fast
PLL 9
FPLL8CLK
FPLL9CLK
Notes to Figure 2–75:
(1) Wire-bond packages support up to 624 Mbps.
(2) See Table 2–38 through 2–41 for the number of channels each device supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels as labeled in the device pin-outs at www.altera.com.
Altera Corporation
July 2005
2–139
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
