Stratix Architecture
The only way you can use the rx_data_alignis if one of the following
is true:
■
■
The receiver PLL is only clocking receive channels (no resources for
the transmitter)
If all channels can fit in one I/O bank
Table 2–38. EP1S30 Differential Channels Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter
/Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter 70
(4)
840
18
35
17
33
19
39
20
40
17
35
16
33
20
39
20
40
20
17
35
16
33
20
39
20
40
20
18
35
17
33
19
39
20
40
(6)
(6)
(6)
(6)
20
20
19
19
20
(6)
(6)
(6)
(6)
20
20
20
20
20
(6)
(6)
(6)
(6)
20
20
20
20
20
(6)
(6)
(6)
(6)
20
20
19
19
20
840 (5)
Receiver
66
840
840 (5)
840
956-pin
BGA
Transmitter 80
(4)
840 (5)
840
Receiver
80
840 (5)
840
1,020-pin
FineLine
BGA
Transmitter
19
(1)
19
(1)
80 (2) (7)
(4)
39
(1)
39
(1)
39
(1)
39
(1)
20
20
20
20
840 (5),(8)
Receiver
840
20
40
20
40
20
40
20 19 (1)
40 19 (1)
20
20
20
20
19 (1)
19 (1)
80 (2) (7)
840 (5),(8)
Table 2–39. EP1S40 Differential Channels (Part 1 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter 68
(4)
840
18
34
17
33
16
34
16
33
16
34
16
33
18
34
17
33
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
840 (5)
Receiver
66
840
840 (5)
Altera Corporation
July 2005
2–133
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
