Stratix Architecture
Table 2–37 shows the number of channels that each fast PLL can clock in
EP1S10, EP1S20, and EP1S25 devices. Tables 2–38 through Table 2–41
show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Transmitter/
Receiver
Total
Channels
Device
Package
PLL 1 PLL 2 PLL 3 PLL 4
EP1S10 484-pin FineLine BGA Transmitter (2)
20
20
36
36
44
44
24
20
48
50
66
66
840 (4)
840 (3)
840 (4)
840 (3)
624 (4)
624 (3)
624 (4)
624 (3)
840 (4)
840 (3)
840 (4)
840 (3)
840 (4)
840 (3)
840 (4)
840 (3)
624 (4)
624 (3)
624 (4)
624 (3)
840 (4)
840 (3)
840 (4)
840 (3)
5
5
5
5
10
5
10
5
10
5
10
5
Receiver
10
9
10
9
10
9
10
9
672-pin FineLine BGA Transmitter (2)
672-pin BGA
18
9
18
9
18
9
18
9
Receiver
780-pin FineLine BGA Transmitter (2)
Receiver
18
11
22
11
22
6
18
11
22
11
22
6
18
11
22
11
22
6
18
11
22
11
22
6
EP1S20 484-pin FineLine BGA Transmitter (2)
Receiver
12
5
12
5
12
5
12
5
10
12
24
13
25
17
33
17
33
10
12
24
12
25
16
33
16
33
10
12
24
12
25
16
33
16
33
10
12
24
13
25
17
33
17
33
672-pin FineLine BGA Transmitter (2)
672-pin BGA
Receiver
780-pin FineLine BGA Transmitter (2)
Receiver
Altera Corporation
July 2005
2–131
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
