High-Speed Differential I/O Support
Table 2–41. EP1S80 Differential Channels (Part 2 of 2) Note (1)
Maximum
Speed
(Mbps)
Center Fast PLLs
Corner Fast PLLs (2), (3)
Transmitter/
Receiver Channels
Total
Package
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
1,508-pin
FineLine
BGA
Transmitter 80 (72)
840
10
10
10
10
20
(8)
20
(8)
20 (8) 20 (8)
(10) (10) (10) (10)
(4)
(7)
20 20 20 20
(20) (20) (20) (20)
20
(8)
20
(8)
20 (8) 20 (8)
840 (5),(8)
Receiver
80 (56)
840
20
20
20
20
10
10
10
10
(14) (14)
10 10
(14) (14)
(14)
(14)
(7)
40
40
40
40
10
(14)
10
(14)
840 (5),(8)
Notes to Tables 2–38 through 2–41:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter
channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also
merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive
both the maximum numbers of receiver and transmitter channels.
(2) Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap,
see the Stratix device pin-outs at www.altera.com.
(3) The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device
pin-outs at www.altera.com.
(4) The numbers of channels listed include the transmitter clock output (tx_outclock) channel. An extra data
channel can be used if a DDR clock is needed.
(5) These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if say PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter
channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent
PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the
device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL.
Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps.
(6) PLLs 7, 8, 9, and 10 are not available in this device.
(7) The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These
channels are independent of the high-speed differential channels. For the location of these channels, see the device
pin-outs at www.altera.com.
(8) See the Stratix device pin-outs at www.altera.com. Channels marked “high” speed are 840 MBps and “low” speed
channels are 462 MBps.
The high-speed differential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■
■
■
■
UTOPIA IV
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
10G Ethernet XSBI
2–136
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
