High-Speed Differential I/O Support
The output levels are compatible with systems of the same voltage as the
power supply (i.e., when VCCIOpins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems). When
VCCIOpins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 2–36 summarizes Stratix MultiVolt I/O support.
Table 2–36. Stratix MultiVolt I/O Support Note (1)
Input Signal (5)
1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
Output Signal (6)
VCCIO (V)
1.5
1.8
2.5
3.3
v
v (2)
v
v
v
v (3)
v (3) v (3)
v (2) v (2)
v (2) v (2)
v
v
v
v
v
v
v
v (2)
v (4) v (3) v (3) v (3)
Notes to Table 2–36:
(1) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V
inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.
(2) The input pin current may be slightly higher than the typical value.
(3) Although VCCIO specifies the voltage necessary for the Stratix device to drive out, a receiving device powered at a
different level can still interface with the Stratix device if it has inputs that tolerate the VCCIO value.
(4) Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.
(5) This is the external signal that is driving the Stratix device.
(6) This represents the system voltage that Stratix supports when a VCCIO pin is connected to a specific voltage level.
For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal
coming out from Stratix is 3.3 V and is compatible with 3.3-V or 5.0-V systems.
Stratix devices contain dedicated circuitry for supporting differential
standards at speeds up to 840 Mbps. The following differential I/O
standards are supported in the Stratix device: LVDS, LVPECL,
HyperTransport, and 3.3-V PCML.
High-Speed
Differential I/O
Support
There are four dedicated high-speed PLLs in the EP1S10 to EP1S25
devices and eight dedicated high-speed PLLs in the EP1S30 to EP1S80
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
f
See the Stratix device pin-outs at www.altera.com for additional high
speed DIFFIO pin information for Stratix devices.
2–130
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
