Stratix Architecture
Table 2–32. I/O Support by Bank (Part 2 of 2)
Top & Bottom Banks
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Left & Right Banks
(1, 2, 5 & 6)
I/O Standard
(3, 4, 7 & 8)
SSTL-3 Class II
v
v
v
v
v
v
v
v
AGP (1× and 2× )
CTT
Each I/O bank has its own VCCIOpins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard
independently. Each bank also has dedicated VREFpins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when VCCIO is 3.3 V, a bank can support
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix devices provide differential on-chip termination (LVDS I/O
standard) to reduce reflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix devices support internal differential termination with a nominal
resistance value of 137.5 Ωfor LVDS input receiver buffers. LVPECL
signals require an external termination resistor. Figure 2–71 shows the
device with differential termination.
Altera Corporation
July 2005
2–127
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
