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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
The external clock outputs do not have their own VCC and ground voltage  
supplies. Therefore, to minimize jitter, do not place switching I/O pins  
next to these output pins. The EP1C3 device in the 100-pin TQFP package  
does not have dedicated clock output pins. The EP1C6 device in the  
144-pin TQFP package only supports dedicated clock outputs from PLL 1.  
Clock Feedback  
Cyclone PLLs have three modes for multiplication and/or phase shifting:  
Zero delay buffer mode The external clock output pin is phase-  
aligned with the clock input pin for zero delay.  
Normal mode If the design uses an internal PLL clock output, the  
normal mode compensates for the internal clock delay from the input  
clock pin to the IOE registers. The external clock output pin is phase  
shifted with respect to the clock input pin if connected in this mode.  
The designer defines which internal clock output from the PLL  
should be phase-aligned to compensate for internal clock delay.  
No compensation mode In this mode, the PLL will not compensate  
for any clock networks.  
Phase Shifting  
Cyclone PLLs have an advanced clock shift capability that enables  
programmable phase shifts. Designers can enter a phase shift (in degrees  
or time units) for each PLL clock output port or for all outputs together in  
one shift. Designers can perform phase shifting in time units with a  
resolution range of 156 to 417 ps. The finest resolution equals one eighth  
of the VCO period. The VCO period is a function of the frequency input  
and the multiplication and division factors. Each clock output counter can  
choose a different phase of the VCO period from up to eight taps.  
Designers can use this clock output counter along with an initial setting  
on the post-scale counter to achieve a phase-shift range for the entire  
period of the output clock. The phase tap feedback to the m counter can  
shift all outputs to a single phase. The Quartus II software automatically  
sets the phase taps and counter settings according to the phase shift  
entered.  
Lock Detect Signal  
The lock output indicates that there is a stable clock output signal in phase  
with the reference clock. Without any additional circuitry, the lock signal  
may toggle as the PLL begins tracking the reference clock. Therefore, the  
designer may need to gate the lock signal for use as a system-control  
signal.  
42  
Altera Corporation  
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