Cyclone FPGA Family Data Sheet
Preliminary Information
Table 9 shows the PLL features in Cyclone devices. Figure 25 shows a
Cyclone PLL.
Table 9. Cyclone PLL Features
Feature
PLL Support
Clock multiplication and division
Phase shift
m/(n × post-scale counter) (1)
Down to 156-ps increments (2), (3)
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Yes
2
One differential or one single-ended (4)
Notes to Table 9:
(1) The m counter ranges from 2 to 32. The n counter and the post-scale counters range
from 1 to 32.
(2) The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
(3) For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
(4) The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Figure 25. Cyclone PLL
Note (1)
VCO Phase Selection
Selectable at Each PLL
Output Port
Post-Scale
Counters
Global clock
÷g0
CLK0 or
LVDSCLK1p (2)
Charge
Pump
Loop
Filter
÷n
∆t
÷g1
÷e
PFD (3)
VCO
Global clock
I/O buffer
CLK1 or
LVDSCLK1n (2)
∆t
÷m
Notes to Figure 25:
(1) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
(2) LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0pin’s
secondary function is LVDSCLK1pand the CLK1pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2pin’s
secondary function is LVDSCLK2pand the CLK3pin’s secondary function is LVDSCLK2n.
(3) PFD: phase frequency detector.
Figure 26 shows the PLL global clock connections.
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Altera Corporation
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