Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 27. Cyclone IOE Structure
Logic Array
OE Register
OE
D
Q
Output Register
Output
D
Q
Combinatorial
input (1)
Input
Input Register
D
Q
Note to Figure 27:
(1) There are two paths available for combinatorial inputs to the logic array. Each path
contains a unique programmable delay chain.
The IOEs are located in I/O blocks around the periphery of the Cyclone
device. There are up to three IOEs per row I/O block and up to three IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column, or direct link interconnects. The column
I/O blocks drive column interconnects. Figure 28 shows how a row I/O
block connects to the logic array. Figure 29 shows how a column I/O
block connects to the logic array.
Altera Corporation
45
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