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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
IOEs support many features, including:  
I/O Structure  
Differential and single-ended I/O standards  
3.3-V, 32-bit, 66-MHz PCI compliance  
Joint Test Action Group (JTAG) boundary-scan test (BST) support  
Output drive strength control  
Weak pull-up resistors during configuration  
Slew-rate control  
Tri-state buffers  
Bus-hold circuitry  
Programmable pull-up resistors in user mode  
Programmable input and output delays  
Open-drain outputs  
DQ and DQS I/O pins  
Cyclone device IOEs contain a bidirectional I/O buffer and three registers  
for complete embedded bidirectional single data rate transfer. Figure 27  
shows the Cyclone IOE structure. The IOE contains one input register, one  
output register, and one output enable register. The designer can use the  
input registers for fast setup times and output registers for fast clock-to-  
output times. Additionally, the designer can use the output enable (OE)  
register for fast clock-to-output enable timing. The Quartus II software  
automatically duplicates a single OE register that controls multiple output  
or bidirectional pins. IOEs can be used as input, output, or bidirectional  
pins.  
44  
Altera Corporation  
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