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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
Slew-Rate Control  
The output buffer for each Cyclone device I/O pin has a programmable  
output slew-rate control that can be configured for low noise or high-  
speed performance. A faster slew rate provides high-speed transitions for  
high-performance systems. However, these fast transitions may  
introduce noise transients into the system. A slow slew rate reduces  
system noise, but adds a nominal delay to rising and falling edges. Each  
I/O pin has an individual slew-rate control, allowing the designer to  
specify the slew rate on a pin-by-pin basis. The slew-rate control affects  
both the rising and falling edges.  
Bus Hold  
Each Cyclone device I/O pin provides an optional bus-hold feature. The  
bus-hold circuitry can hold the signal on an I/O pin at its last-driven  
state. Since the bus-hold feature holds the last-driven state of the pin until  
the next input signal is present, an external pull-up or pull-down resistor  
is not necessary to hold a signal level when the bus is tri-stated.  
The bus-hold circuitry also pulls undriven pins away from the input  
threshold voltage where noise can cause unintended high-frequency  
switching. The designer can select this feature individually for each I/O  
pin. The bus-hold output will drive no higher than VCCIO to prevent  
overdriving signals. If the bus-hold feature is enabled, the device cannot  
use the programmable pull-up option. Disable the bus-hold feature when  
the I/O pin is configured for differential signals.  
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of  
approximately 7 kΩto pull the signal level to the last-driven state.  
Table 4–15 on page 4–6 gives the specific sustaining current for each  
VCCIO voltage level driven through this resistor and overdrive current  
used to identify the next-driven input level.  
The bus-hold circuitry is only active after configuration. When going into  
user mode, the bus-hold circuit captures the value on the pin present at  
the end of configuration.  
Programmable Pull-Up Resistor  
Each Cyclone device I/O pin provides an optional programmable pull-  
up resistor during user mode. If the designer enables this feature for an  
I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the  
VCCIO level of the output pin's bank. Dedicated clock pins do not have the  
optional programmable pull-up resistor.  
Altera Corporation  
January 2007  
2–51  
Preliminary  
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