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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Global Clock Network & Phase-Locked Loops  
Single-Port Mode  
The M4K memory blocks also support single-port mode, used when  
simultaneous reads and writes are not required. See Figure 2–21. A single  
M4K memory block can support up to two single-port mode RAM blocks  
if each RAM block is less than or equal to 2K bits in size.  
Figure 2–21. Single-Port Mode  
Note (1)  
6 LAB Row  
Clocks  
RAM/ROM  
6
256 × 16  
512 × 8  
1,024 × 4  
data[ ]  
D
ENA  
Q
Data In  
2,048 × 2  
4,096 × 1  
To MultiTrack  
Interconnect  
Data Out  
D
Q
ENA  
address[ ]  
Address  
D
Q
ENA  
wren  
Write Enable  
outclken  
D
ENA  
Q
inclken  
inclock  
Write  
Pulse  
Generator  
outclock  
Note to Figure 2–21:  
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both  
read and write operations.  
Cyclone devices provide a global clock network and up to two PLLs for a  
complete clock management solution.  
Global Clock  
Network &  
Phase-Locked  
Loops  
Global Clock Network  
There are four dedicated clock pins (CLK[3..0], two pins on the left side  
and two pins on the right side) that drive the global clock network, as  
shown in Figure 2–22. PLL outputs, logic array, and dual-purpose clock  
(DPCLK[7..0]) pins can also drive the global clock network.  
Altera Corporation  
January 2007  
2–29  
Preliminary  
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