Cyclone Device Handbook, Volume 1
Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode
Note (1), (2)
6 LAB Row Clocks
6
6
Memory Block
256 × 16 (2)
512 × 8
A
B
dataA[ ]
dataB[ ]
Data In
Q
Q
Q
D
D
Q
Q
Q
Data In
ENA
ENA
1,024 × 4
2,048 × 2
4,096 × 1
byteenaA[ ]
byteenaB[ ]
Byte Enable A
D
D
Byte Enable B
ENA
ENA
addressA[ ]
addressB[ ]
Address A
Address B
D
D
ENA
ENA
wrenA
wrenB
Write/Read
Enable
Write/Read
Enable
Write
Pulse
Generator
Write
Pulse
Generator
Q
D
D
Q
clkenA
clockA
ENA
ENA
Data Out
Data Out
clkenB
clockB
D
Q
Q
D
ENA
ENA
qA[ ] qB[ ]
Notes to Figure 2–18:
(1) All registers shown have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
2–26
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
