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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Embedded Memory  
Independent Clock Mode  
The M4K memory blocks implement independent clock mode for true  
dual-port memory. In this mode, a separate clock is available for each port  
(ports A and B). Clock A controls all registers on the port A side, while  
clock B controls all registers on the port B side. Each port, A and B, also  
supports independent clock enables and asynchronous clear signals for  
port A and B registers. Figure 2–17 shows an M4K memory block in  
independent clock mode.  
Figure 2–17. Independent Clock Mode  
Notes (1), (2)  
6 LAB Row Clocks  
Memory Block  
256 ´ 16 (2)  
512 ´ 8  
1,024 ´ 4  
2,048 ´ 2  
A
B
6
6
dataA[ ]  
dataB[ ]  
Data In  
Q
Q
D
D
Q
Q
Data In  
ENA  
ENA  
4,096 ´ 1  
byteenaA[ ]  
byteenaB[ ]  
Byte Enable A  
D
D
Byte Enable B  
ENA  
ENA  
addressA[ ]  
addressB[ ]  
Address A  
Address B  
Q
Q
D
D
Q
Q
ENA  
ENA  
wrenA  
wrenB  
Write/Read  
Enable  
Write/Read  
Enable  
D
D
Write  
Pulse  
Generator  
Write  
Pulse  
Generator  
clkenA  
clockA  
clkenB  
clockB  
ENA  
ENA  
Data Out  
Data Out  
D
Q
Q
D
ENA  
ENA  
qA[ ] qB[ ]  
Notes to Figure 2–17:  
(1) All registers shown have asynchronous clear ports.  
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both  
read and write operations.  
Input/Output Clock Mode  
Input/output clock mode can be implemented for both the true and  
simple dual-port memory modes. On each of the two ports, A or B, one  
clock controls all registers for inputs into the memory block: data input,  
wren, and address. The other clock controls the block's data output  
registers. Each memory block port, A or B, also supports independent  
clock enables and asynchronous clear signals for input and output  
registers. Figures 2–18 and 2–19 show the memory block in input/output  
clock mode.  
Altera Corporation  
January 2007  
2–25  
Preliminary  
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