Cyclone Device Handbook, Volume 1
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. You can use up to two clocks in this mode. The write
clock controls the block's data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 2–20 shows a memory block in read/write clock mode.
Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2)
6 LAB Row
Clocks
Memory Block
256 × 16
512 × 8
6
1,024 × 4
data[ ]
D
ENA
Q
Data In
2,048 × 2
4,096 × 1
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
Read Address
D
Q
Q
Q
ENA
wraddress[ ]
Write Address
Byte Enable
Read Enable
D
ENA
byteena[ ]
D
ENA
rden
D
Q
ENA
wren
rdclken
Write
Pulse
Generator
D
ENA
Q
wrclken
wrclock
Write Enable
rdclock
Notes to Figure 2–20:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
2–28
Preliminary
Altera Corporation
January 2007
ALTERA [ ALTERA CORPORATION ]
