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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Global Clock Network & Phase-Locked Loops  
Dual-Purpose Clock Pins  
Each Cyclone device except the EP1C3 device has eight dual-purpose  
clock pins, DPCLK[7..0](two on each I/O bank). EP1C3 devices have  
five DPCLKpins in the 100-pin TQFP package. These dual-purpose pins  
can connect to the global clock network (see Figure 2–22) for high-fanout  
control signals such as clocks, asynchronous clears, presets, and clock  
enables, or protocol control signals such as TRDYand IRDYfor PCI, or  
DQS signals for external memory interfaces.  
Combined Resources  
Each Cyclone device contains eight distinct dedicated clocking resources.  
The device uses multiplexers with these clocks to form six-bit buses to  
drive LAB row clocks, column IOE clocks, or row IOE clocks. See  
Figure 2–23. Another multiplexer at the LAB level selects two of the six  
LAB row clocks to feed the LE registers within the LAB.  
Figure 2–23. Global Clock Network Multiplexers  
Column I/O Region  
IO_CLK]5..0]  
Global Clock  
Network  
Global Clocks [3..0]  
Dual-Purpose Clocks [7..0]  
Clock [7..0]  
LAB Row Clock [5..0]  
PLL Outputs [3..0]  
Core Logic [7..0]  
Row I/O Region  
IO_CLK[5..0]  
IOE clocks have row and column block regions. Six of the eight global  
clock resources feed to these row and column regions. Figure 2–24 shows  
the I/O clock regions.  
Altera Corporation  
January 2007  
2–31  
Preliminary  
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