欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1C20F400C7ES的Datasheet PDF文件第32页浏览型号EP1C20F400C7ES的Datasheet PDF文件第33页浏览型号EP1C20F400C7ES的Datasheet PDF文件第34页浏览型号EP1C20F400C7ES的Datasheet PDF文件第35页浏览型号EP1C20F400C7ES的Datasheet PDF文件第37页浏览型号EP1C20F400C7ES的Datasheet PDF文件第38页浏览型号EP1C20F400C7ES的Datasheet PDF文件第39页浏览型号EP1C20F400C7ES的Datasheet PDF文件第40页  
Cyclone Device Handbook, Volume 1  
The eight global clock lines in the global clock network drive throughout  
the entire device. The global clock network can provide clocks for all  
resources within the device IOEs, LEs, and memory blocks. The global  
clock lines can also be used for control signals, such as clock enables and  
synchronous or asynchronous clears fed from the external pin, or DQS  
signals for DDR SDRAM or FCRAM interfaces. Internal logic can also  
drive the global clock network for internally generated global clocks and  
asynchronous clears, clock enables, or other control signals with large  
fanout. Figure 2–22 shows the various sources that drive the global clock  
network.  
Figure 2–22. Global Clock Generation  
Note (1)  
DPCLK2  
DPCLK3  
Cyclone Device  
Global Clock  
Network  
8
DPCLK1  
DPCLK4  
From logic  
array  
From logic  
array  
4
4
CLK0  
CLK2  
PLL2  
(2)  
PLL1  
2
CLK1 (3)  
CLK3 (3)  
4
4
2
DPCLK0  
DPCLK5  
DPCLK7  
DPCLK6  
Notes to Figure 2–22:  
(1) The EP1C3 device in the 100-pin TQFP package has five DPCLKpins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and  
DPCLK7).  
(2) EP1C3 devices only contain one PLL (PLL 1).  
(3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1and CLK3.  
2–30  
Preliminary  
Altera Corporation  
January 2007  
 复制成功!