Chapter 4: DC and Switching Characteristics
4–95
Duty Cycle Distortion
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)
I/O Standards
Drive Strength
–6 Speed Grade
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.5 V
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
373
467
467
327
420
561
420
467
233
467
467
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.2-V HSTL
DIFFERENTIAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
SSTL CLASS I
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
327
420
561
420
467
233
MHz
MHz
MHz
MHz
MHz
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.2-V
HSTL
Duty Cycle Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from
its ideal position. The ideal position is when both the clock high time (CLKH) and the
clock low time (CLKL) equal half of the clock period (T), as shown in Figure 4–10.
DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as
D1 for the falling edge A and D2 for the falling edge B (refer to Figure 4–10). The
maximum DCD for a clock is the larger value of D1 and D2.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
