Chapter 4: DC and Switching Characteristics
4–97
Duty Cycle Distortion
Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block.
As the PLL only monitors the positive edge of the reference clock input and internally
re-creates the output clock signal, any DCD present on the reference clock is filtered
out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than
the DCD for a DDIO output without PLL in the clock path.
Table 4–108 through Table 4–113 show the maximum DCD in absolution derivation
for different I/O standards on Arria GX devices. Examples are also provided that
show how to calculate DCD as a percentage.
Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins
Maximum DCD (ps) for Non-DDIO Output
Row I/O Output Standard
–6 Speed Grade
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
275
155
135
180
195
145
125
85
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
100
115
80
Here is an example for calculating the DCD as a percentage for a non-DDIO output on
a row I/O:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 125 ps
(see Table 4–109). If the clock frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
