TriMatrix Memory
Table 2–12 shows the input and output data signal connections along
with the address and control signal input connections to the row unit
interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals
Unit Interface Block
Input Signals
Output Signals
L0
datain_a[14..0]
byteena_a[1..0]
dataout_a[11..0]
L1
L2
datain_a[29..15]
byteena_a[3..2]
dataout_a[23..12]
dataout_a[35..24]
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
L3
L4
L5
R0
R1
R2
addressa[15..5]
datain_a[41..36]
dataout_a[47..36]
dataout_a[59..48]
dataout_a[71..60]
dataout_b[11..0]
dataout_b[23..12]
dataout_b[35..24]
datain_a[56..42]
byteena_a[5..4]
datain_a[71..57]
byteena_a[7..6]
datain_b[14..0]
byteena_b[1..0]
datain_b[29..15]
byteena_b[3..2]
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
R3
R4
R5
addressb[15..5]
datain_b[41..36]
dataout_b[47..36]
dataout_b[59..48]
dataout_b[71..60]
datain_b[56..42]
byteena_b[5..4]
datain_b[71..57]
byteena_b[7..6]
f
For more information about TriMatrix memory, refer to the TriMatrix
Embedded Memory Blocks in Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook.
2–70
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
