Arria GX Architecture
resources. Up to 16 direct link input connections to the M4K RAM block
are possible from the left adjacent LABs and another 16 are possible from
the right adjacent LAB. M4K RAM block outputs can also connect to left
and right LABs through direct link interconnect. Figure 2–45 shows the
M4K RAM block to logic array interface.
Figure 2–45. M4K RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
datain
byte
enable
control
signals
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
Altera Corporation
May 2008
2–65
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
