Arria GX Architecture
Table 2–11. TriMatrix Memory Features (Part 2 of 2)
M512 RAM Block
Memory Feature
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
(32 × 18 Bits)
Simple dual-port memory
mixed width support
v
v
v
v
v
True dual-port memory
mixed width support
Power-up conditions
Register clears
Outputs cleared
Output registers
Outputs cleared
Output registers
Outputs unknown
Output registers
Unknown output
Mixed-port read-during-write Unknown output/old data Unknown output/old data
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
Altera Corporation
May 2008
2–61
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
