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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Arria GX Architecture  
The Quartus II Compiler automatically creates carry chain logic during  
compilation, or you can create it manually during design entry.  
Parameterized functions such as LPM functions automatically take  
advantage of carry chains for the appropriate functions. The Quartus II  
Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or  
shared arithmetic mode) by linking LABs together automatically. For  
enhanced fitting, a long carry chain runs vertically allowing fast  
horizontal connections to TriMatrix memory and DSP blocks. A carry  
chain can continue as far as a full column. To avoid routing congestion in  
one small area of the device when a high fan-in arithmetic function is  
implemented, the LAB can support carry chains that only utilize either  
the top half or bottom half of the LAB before connecting to the next LAB.  
The other half of the ALMs in the LAB is available for implementing  
narrower fan-in functions in normal mode. Carry chains that use the top  
four ALMs in the first LAB carries into the top half of the ALMs in the  
next LAB within the column. Carry chains that use the bottom four ALMs  
in the first LAB carries into the bottom half of the ALMs in the next LAB  
within the column. Every other column of the LABs are top-half  
bypassable, while the other LAB columns are bottom-half bypassable.  
Refer to “MultiTrack Interconnect” on page 2–54 for more information  
about carry chain interconnect.  
Shared Arithmetic Mode  
In shared arithmetic mode, the ALM can implement a three-input add. In  
this mode, the ALM is configured with four 4-input LUTs. Each LUT  
either computes the sum of three inputs or the carry of three inputs. The  
output of the carry computation is fed to the next adder (either to adder1  
in the same ALM or to adder0of the next ALM in the LAB) using a  
dedicated connection called the shared arithmetic chain. This shared  
arithmetic chain can significantly improve the performance of an adder  
tree by reducing the number of summation stages required to implement  
an adder tree. Figure 2–36 shows the ALM in shared arithmetic mode.  
Altera Corporation  
May 2008  
2–49  
Arria GX Device Handbook, Volume 1  
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