Arria GX Architecture
using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. Asynchronous load data for
the register comes from the dataeor datafinput of the ALM. ALMs in
normal mode support register packing.
Figure 2–32. Six-Input Function in Normal Mode Notes (1), (2)
To general or
local routing
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
To general or
local routing
D
D
Q
reg0
datae1
dataf1
(2)
To general or
local routing
Q
These inputs are available for register packing.
reg1
Notes to Figure 2–32:
(1) If datae1and dataf1are used as inputs to the six-input function, datae0and
dataf0are available for register packing.
(2) The dataf1input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input
functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-
input functions sharing four inputs. Figure 2–33 shows the template of
supported seven-input functions utilizing extended LUT mode. In this
mode, if the seven-input function is unregistered, the unused eighth
input is available for register packing. Functions that fit into the template
shown in Figure 2–33 occur naturally in designs. These functions often
appear in designs as “if-else” statements in Verilog HDL or VHDL code.
Altera Corporation
May 2008
2–45
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
