Arria GX Architecture
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
carry_in = '0'
3-Bit Add Example
ALM Implementation
ALM 1
X2 X1 X0
Y2 Y1 Y0
Z2 Z1 Z0
3-Input S0
1st stage add is
implemented in LUTs.
LUT
+
R0
2nd stage add is
implemented in adders.
S2 S1 S0
C2 C1 C0
X0
Y0
Z0
3-Input
LUT
+
C0
S1
R3 R2 R1 R0
X1
Y1
Z1
3-Input
LUT
Decimal
Equivalents
Binary Add
R1
1
1
0
1
0
1
0
1
0
6
5
C1
3-Input
LUT
2
+
+
0
1
0
0
1
1
+
+
1
1
2 x 6
13
ALM 2
1
0
1
S2
C2
'0'
3-Input
LUT
R2
X2
Y2
Z2
3-Input
LUT
3-Input
LUT
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain
available in shared arithmetic mode allows the ALM to implement a
three-input add, which significantly reduces the resources necessary to
implement large adder trees or correlator functions. Shared arithmetic
chains can begin in either the first or fifth ALM in a LAB. The Quartus II
Compiler automatically links LABs to create shared arithmetic chains
longer than 16 (8 ALMs in arithmetic or shared arithmetic mode). For
enhanced fitting, a long shared arithmetic chain runs vertically allowing
Altera Corporation
May 2008
2–51
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
