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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Adaptive Logic Modules  
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode  
datae0  
datac  
dataa  
5-Input  
LUT  
datab  
To general or  
local routing  
datad  
dataf0  
combout0  
To general or  
local routing  
D
Q
5-Input  
LUT  
reg0  
datae1  
dataf1  
(1)  
This input is available  
for register packing.  
Note to Figure 2–33:  
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second  
register, reg1, is not available.  
Arithmetic Mode  
Arithmetic mode is ideal for implementing adders, counters,  
accumulators, wide parity functions, and comparators. An ALM in  
arithmetic mode uses two sets of 2 four-input LUTs along with two  
dedicated full adders. The dedicated adders allow the LUTs to be  
available to perform pre-adder logic; therefore, each adder can add the  
output of two four-input functions. The four LUTs share the dataaand  
databinputs. As shown in Figure 2–34, the carry-in signal feeds to  
adder0, and the carry-out from adder0feeds to carry-in of adder1. The  
carry-out from adder1drives to adder0of the next ALM in the LAB.  
ALMs in arithmetic mode can drive out registered and/or unregistered  
versions of the adder outputs.  
2–46  
Altera Corporation  
May 2008  
Arria GX Device Handbook, Volume 1  
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