Transceivers
Serial Loopback
Figure 2–18 shows the transceiver data path in serial loopback.
Figure 2–18. Transceiver Data Path in Serial Loopback
Transmitter PCS
Transmitter PMA
TX Phase
Compen-
sation
Byte
Serializer
8B/10B
Encoder
Serializer
FIFO
PLD
Logic
Array
Serial Loopback
Receiver PMA
Receiver PCS
RX Phase
Compen-
sation
Clock
Recovery
Unit
De-
Serializer
Rate
Match
FIFO
Byte
De-
Serializer
8B/10B
Decoder
Word
Aligner
FIFO
In GIGE and Serial RapidIO modes, you can dynamically put each
transceiver channel individually in serial loopback by controlling the
rx_seriallpbkenport. A high on the rx_seriallpbkenport puts
the transceiver into serial loopback and a low takes the transceiver out of
serial loopback.
As seen in Figure 2–18, the serial data output from the transmitter
serializer is looped back to the receiver CRU in serial loopback. The
transmitter data path from the PLD interface to the serializer in serial
loopback is the same as in non-loopback mode. The receiver data path
from the clock recovery unit to the PLD interface in serial loopback is the
same as in non-loopback mode. Since the entire transceiver data path is
available in serial loopback, this option is often used to diagnose the data
path as a probable cause of link errors.
1
When serial loopback is enabled, the transmitter output buffer is
still active and drives the serial data out on the tx_dataout
port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver.
An external source (pattern generator or transceiver) generates the source
data. The high-speed serial source data arrives at the high-speed
differential receiver input buffer, passes through the CRU unit and the
retimed serial data is looped back, and is transmitted though the
high-speed differential transmitter output buffer.
Figure 2–19 shows the data path in reverse serial loopback mode.
2–26
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
