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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Arria GX Architecture  
GIGE Mode Rate Matcher  
In GIGE mode, the rate matcher can compensate up to 100 PPM  
(200 PPM total) frequency difference between the upstream transmitter  
and the receiver. The rate matcher logic inserts or deletes /I2/ idle  
ordered sets to/from the rate matcher FIFO during the inter-frame or  
inter-packet gap (IFG or IPG). /I2/ is selected as the rate matching  
ordered set since it maintains the running disparity, unlike /I1/ that  
alters the running disparity. Since the /I2/ ordered-set contains two  
10-bit code groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a  
time for rate matching.  
1
The rate matcher logic has the capability to insert or delete /C1/  
or /C2/ configuration ordered sets when ‘GIGE Enhanced’  
mode is chosen as the sub-protocol in the MegaWizard Plug-In  
Manager.  
If the frequency PPM difference between the upstream transmitter and  
the local receiver is high, or if the packet size is too large, the rate matcher  
FIFO buffer can face an overflow or underflow situation.  
Basic Mode  
In Basic mode, you can program the skip and control pattern for rate  
matching. There is no restriction on the deletion of a skip character in a  
cluster. The rate matcher deletes the skip characters as long as they are  
available. For insertion, the rate matcher inserts skip characters such that  
the number of skip characters at the output of rate matcher does not  
exceed five.  
8B/10B Decoder  
The 8B/10B decoder is used in all supported functional modes. The  
8B/10B decoder takes in 10-bit data from the rate matcher and decodes it  
into 8-bit data + 1-bit control identifier, thereby restoring the original  
transmitted data at the receiver. The 8B/10B decoder indicates whether  
the received 10-bit character is a data or control code through the  
rx_ctrldetectport. If the received 10-bit code group is a control  
character (Kx.y), the rx_ctrldetectsignal is driven high and if it is a  
data character (Dx.y), the rx_ctrldetectsignal is driven low.  
Altera Corporation  
May 2008  
2–23  
Arria GX Device Handbook, Volume 1  
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