Transceivers
Table 2–5 shows the maximum frequency difference that the rate matcher
can tolerate in XAUI, PCI Express (PIPE), GIGE, and Basic functional
modes.
Table 2–5. Rate Matcher PPM Tolerance
Function Mode
PPM
XAUI
PCI Express (PIPE)
GIGE
100
300
100
300
Basic
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
PCI Express (PIPE) Mode Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to
300 PPM (600 PPM total) frequency difference between the upstream
transmitter and the receiver. The rate matcher logic looks for skip ordered
sets (SOS), which contains a /K28.5/ comma followed by three /K28.0/
skip characters. The rate matcher logic deletes or inserts /K28.0/ skip
characters as necessary from/to the rate matcher FIFO.
The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow
and underflow protection. In the event of a FIFO buffer overflow, the rate
matcher deletes any data after detecting the overflow condition to
prevent FIFO pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer can
gracefully exit the overflow and underflow condition without requiring a
FIFO reset. The rate matcher FIFO overflow and underflow condition is
indicated on the pipestatusport.
You can bypass the rate matcher in PCI Express (PIPE) mode if you have
a synchronous system where the upstream transmitter and local receiver
derive their reference clocks from the same source.
2–22
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
