Arria GX Architecture
deactivated, the rx_syncstatussignal acts as a re-synchronization
signal to signify that the alignment pattern has been detected but not
locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus
signal indicates the link status. If the rx_syncstatussignal is high, link
synchronization is achieved. If the rx_syncstatussignal is low, link
synchronization has not yet been achieved, or there were enough code
group errors to lose synchronization.
f
For more information about manual alignment modes, refer to the
Arria GX Device Handbook.
The rx_patterndetectsignal pulses high during a new alignment
and whenever the alignment pattern occurs on the current word
boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter.
Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user
programmable value, the rx_rlvsignal goes high for a minimum pulse
width of two recovered clock cycles. The maximum run values supported
are 128 UI for 8-bit serialization or 160 UI for 10-bit serialization.
Running Disparity Check
The running disparity error rx_disperrand running disparity value
rx_runningdispare sent along with aligned data from the 8B/10B
decoder to the FPGA. You can ignore or act on the reported running
disparity value and running disparity error signals.
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in
bit-slip mode.
Altera Corporation
May 2008
2–19
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
