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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Transceivers  
The clock recovery unit controls whether the receiver PLL locks to the  
input reference clock (lock-to-reference mode) or the incoming serial data  
(lock-to data mode). You can set the CRU to switch between lock-to-data  
and lock-to-reference modes automatically or manually. In automatic  
lock mode, the phase detector and dedicated parts per million (PPM)  
detector within each receiver channel control the switch between  
lock-to-data and lock-to-reference modes based on some pre-set  
conditions. In manual lock mode, you control the switch manually using  
the rx_locktorefclkand rx_locktodatasignals.  
f
For more details, refer to the Clock Recovery Unit section in the Arria GX  
Transceiver Protocol Support and Additional Features chapter in volume 2 of  
the Arria GX Device Handbook.  
Table 2–4 show the behavior of THE CRU block with respect to the  
rx_locktorefclkand rx_locktodatasignals.  
Table 2–4. CRU Manual Lock Signals  
rx_locktorefclk  
rx_locktodata  
CRU Mode  
1
x
0
0
1
0
Lock-to-reference clock  
Lock-to-data  
Automatic  
If the rx_locktorefclkand rx_locktodataports are not used, the  
default is automatic lock mode.  
Deserializer  
The deserializer block clocks in serial input data from the receiver buffer  
using the high-speed serial recovered clock and deserializes into 8- or  
10-bit parallel data using the low-speed parallel recovered clock. The  
serial data is assumed to be received with LSB first, followed by MSB. It  
feeds the deserialized 8- or 10-bit data to the word aligner, as shown in  
Figure 2–14.  
2–16  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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