Arria GX Architecture
generates two clocks: a high-speed serial recovered clock that clocks the
deserializer and a low-speed parallel recovered clock that clocks the
receiver's digital logic.
Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.
Figure 2–13. Receiver PLL and Clock Recovery Unit
/M
rx_pll_locked
CP+LF
Dedicated
REFCLK0
/2
/2
up
dn
PFD
Dedicated
REFCLK1
VCO
/L
rx_cruclk
up
dn
Inter-Transceiver Lines [2:0]
Global Clock (2)
rx_freqlocked
rx_locktorefclk
(
)
Clock Recovery Unit CRU Control
rx_locktodata
rx_datain
High-speed serial recovered clk
Low-speed parallel recovered clk
Notes to Figure 2–13:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the
necessary /M and /L dividers.
(2) The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
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One of the two available dedicated reference clock input pins
(REFCLK0or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
All the parameters listed are programmable in the Quartus II software.
The receiver PLL has the following features:
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Operates from 600 Mbps to 3.125 Gbps.
Uses a reference clock between 50 MHz and 622.08 MHz.
Programmable bandwidth settings: low, medium, and high.
Programmable rx_locktorefclk(forces the receiver PLL to lock
to reference clock) and rx_locktodata(forces the receiver PLL to
lock to data).
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The voltage-controlled oscillator (VCO) operates at half rate.
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and
25. Not all settings are supported for any particular frequency.
Two lock indication signals are provided. They are found in PFD
mode (lock-to-reference clock), and PD (lock-to-data).
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Altera Corporation
May 2008
2–15
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
