Arria GX Architecture
Figure 2–14. Deserializer Note (1)
Received Data
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
To Word
Aligner
Clock
Recovery
Unit
High-speed serial recovered clock
Low-speed parallel recovered clock
Note to Figure 2–14:
(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer
ignores protocol symbol boundaries when converting this data.
Therefore, the boundaries of the transferred words are arbitrary. The
word aligner aligns the incoming data based on specific byte or word
boundaries. The word alignment module is clocked by the local receiver
recovered clock during normal operation. All the data and programmed
patterns are defined as “big-endian” (most significant word followed by
least significant word). Most-significant-bit-first protocols should reverse
the bit order of word align patterns programmed.
This module detects word boundaries for 8B/10B-based protocols. This
module is also used to align to specific programmable patterns in
PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align
word boundaries using a single 7- or 10-bit pattern. The pattern detector
can either do an exact match, or match the exact pattern and the
Altera Corporation
May 2008
2–17
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
