External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–9. DQS Phase-Shift Circuitry and DQS Logic Block Connections
Note (1)
Notes to Figure 3–9:
(1) All features of the DQS phase-shift circuitry and the DQS logic block are accessible from the altdqsmegafunction
in the Quartus II software. You should, however, use Altera’s memory controller IP Tool Bench to generate the data
path for your memory interface.
(2) DQS logic block is available on every DQS and DQSn pin.
(3) There is one DQS phase-shift circuit on the top and bottom side of the device.
(4) The input reference clock can come from CLK[15..12]por PLL 5 for the DQS phase-shift circuitry on the top side
of the device or from CLK[7..4]por PLL 6 for the DQS phase-shift circuitry on the bottom side of the device.
(5) Each individual DQS and DQSn pair can have individual DQS delay settings to and from the logic array.
(6) This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
3–23
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
