Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–8. DQS and DQSn Pins and the DQS Phase-Shift Circuitry
Note (1)
From PLL 5 (3)
CLK[15..12]p (2)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Phase-Shift
Circuitry
DQS Logic
Blocks
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Notes to Figure 3–8:
(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II or Stratix II GX
device, up to 8 on the left side of the DQS phase-shift circuitry (I/O banks 3 and 8), and up to 10 on the right side
(I/O bank 4 and 7).
(2) Clock pins CLK[15..12]pfeed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]pfeed
the phase-shift circuitry on the bottom of the device. You can also use a phase-locked loop (PLL) clock output as a
reference clock to the phase-shift circuitry. The reference clock can also be used in the logic array.
(3) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Figure 3–9 shows the connections between the DQS phase-shift circuitry
and the DQS logic block.
3–22
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
