PLLs in Stratix II and Stratix II GX Devices
Figures 1–52 and 1–53 show the global clock and regional clock select
blocks, respectively.
Figure 1–52. Stratix II Global Clock Control Block
CLKp
Pins
2
PLL Counter
Outputs
2
CLKn
Pin
Internal
Logic
2
CLKSELECT[1..0]
(1)
Static Clock
Select (2)
This Multiplexer
Supports User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 1–52:
(1) These clock select signals can only be dynamically controlled through internal
logic when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file and cannot
be dynamically controlled during user-mode operation.
Altera Corporation
July 2009
1–87
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
